RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
8
Boot-Mode Settings
The RM7965A operating modes are initialized at power-up by the boot-time mode control
interface. The serial boot-time mode control interface operates at a very low frequency
(SysClock divided by 256), allowing the initialization information to be kept in a low cost
EPROM or system interface ASIC.
The boot-time serial mode stream is defined below. Bit 0 is presented to the processor as the
first bit in the stream following VccOK being asserted. Bit 255 is the last bit transferred. An
automated mode bit generation tool (program that runs on a PC) is available on the PMC-Sierra
website.
Name
Size Field
Description
Reserved
preBigEndian
1
1
0
1
Must be set to 0.
Places the processor in big endian mode.
0: Little Endian (Little)
1: Big Endian (Big)
SI32Wide
1
1
2
2
Sets the SysAD interface width to 32 bits.
0: 64-bit SysAD (SADSz64)
1: 32-bit SysAD (SADSz32)
SADRdOverlap
SADWrProt[1:0]
3
Enables overlapping reads on the SysAD interface.
0: Overlap disabled (OvlpDisabled)
1: Overlap enabled (OvlpEnabled)
5:4
SysAD interface write protocol.
00: R4000 compatible (R4000)
01: Reserved
10: Pipelined writes (Pipelined)
11: Write re-issue (ReIssue)
SADDatRate[3:0]
4
9:6
SysAD interface write transmit data rate.
0000: Dd
0001: Ddx
0010: Ddxx
0011: Dxdx
0100: Ddxxx
0101: Ddxxxx
0110: Dxxdxx
0111: Ddxxxxxx
1000: Dxxxdxxx
1001-1111: Reserved
ECacheEn
ECBurstMd
1
1
10
11
Enables the external cache.
0: ECache Disabled
1: ECache Enabled
Sets ECache protocol for burst mode RAMs.
0: Dual Cycle Deselect, (DCD),
1: Single Cycle Deselect, (SCD).
Reserved
Reserved
1
1
12
13
Must be set to 0.
Must be set to 0.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
48
PMC [ PMC-SIERRA, INC ]
