RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Figure 10 Multiple Outstanding Reads
Processor
Tertiary(Miss)
System
Processor
Addr
Tertiary(Miss)
Data0 Data1
System
Master
2
5
SysClock
Data0
Addr
Data0 Data1
Data1
2
2
1
2
SysAD
Read
Read
2
NData
NData
SysCmd
RspSwap*
1
7
ValidOut*
ValidIn*
8
Release*
PRqst*
3
4
PAck*
6
1
TcMatch
6.5 Write Modes
The RM7965A implements two write modes: Pipeline Writes and Write Reissue. Pipelined
write mode eliminates these two wait states by allowing the processor to drive a new write
address onto the bus immediately after the previous data cycle. This allows for higher SysAD
bus utilization. At high frequencies the processor may drive a subsequent write onto the bus
prior to the time the external agent deasserts WrRdy*, indicating that it can not accept another
write cycle. This can cause the cycle to be missed.
Write reissue mode is an enhancement to pipelined write mode and allows the processor to
reissue missed write cycles. If WrRdy* is deasserted during the issue phase of a write
operation, the cycle is aborted by the processor and reissued at a later time.
In write reissue mode, a rate of one write every two bus cycles can be achieved. Pipelined
writes have the same two bus cycle write repeat rate, but can issue one additional write
following the deassertion of WrRdy*.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
43
PMC [ PMC-SIERRA, INC ]
