RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
PerfControl
Field
Description
7:5
8
Reserved (must be zero)
Count in Kernel Mode
0:
1:
Disable
Enable
9
Count in User Mode
0:
1:
Disable
Enable
10
Count Enable
0:
1:
Disable
Enable
31:11
Reserved (must be zero)
The performance counter interrupt only occurs when interrupts are enabled in the Status
register, IE=1, and the Interrupt Mask bit 13 (IM13) of the coprocessor 0 interrupt control
register is set. The performance counter shares this interrupt with the 64-entry branch Trace
Buffer.
Since a performance counter can be set up to count clock cycles, it can be used as either a
second timer, or a watchdog interrupt. A watchdog interrupt can be used as an aid in debugging
system or software “hangs.” Typically the software is set up to periodically update the count so
that no interrupt occurs. When a hang occurs the interrupt ultimately triggers, thereby breaking
free from the hang-up.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
47
PMC [ PMC-SIERRA, INC ]
