RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Figure 10 shows a typical RM7965A sequence resulting in two outstanding reads as explained
in the following sequence:
1. The processor issues a read.
2. The external agent takes control of the bus in preparation for returning data to the processor.
3. The processor encounters another internal cache miss and therefore asserts PRqst* in order
to regain control of the bus.
4. The external agent pulses PAck*, returning control of the bus to the processor.
5. The processor issues a read for the second miss.
6. The RspSwap* pin is asserted to denote the out of order response. Not shown in the figure
is the completion of the data transfer for the second miss, or any of the data transfer for the
first miss.
7. The external agent retakes control of the bus and begins returning data (out of order) for the
second miss to the processor
Figure 9 Processor Block Write
SysClock
SysAD
Addr
Write
Data0
NData
Data1
NData
Data2
NData
Data3
NEOD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
42
PMC [ PMC-SIERRA, INC ]
