RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
6.4 System Interface Operation
To support non-blocking caches and data prefetch instructions, the RM7965A allow two
outstanding reads. An external agent may respond to read requests in whatever order it chooses
by using the response order indicator pin RspSwap*. No more than two read requests are
outstanding to the external agent. Support for multiple outstanding reads can be enabled or
disabled via a boot- time mode bit. Refer to Section 8 for a complete list of mode bits.
The RM7965A can issue read and write requests to an external agent, while an external agent
can issue null and read responses to the RM7965A.
For processor reads, the RM7965A asserts ValidOut* and simultaneously drives the address
and read command on the SysAD and SysCmd buses. If the system interface has RdRdy*
asserted, then the processor tristates its drivers and signals the release of the system interface to
slave state by asserting Release*. The external agent can then begin sending data to the
RM7965A.
Figure 8 shows a processor block read request and the external agent read response for a
system.
Figure 8 Processor Block Read
SysClock
SysAD
Addr
Read
Data0
NData
Data1
NData
Data3
NEOD
Data2
NData
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
In Figure 8 the read latency is 4 cycles (ValidOut* to ValidIn*), and the response data pattern
is DDxxDD. Figure 9 shows a processor block write where the processor was programmed with
write-back data rate boot code 2, or DDxxDDxx.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
41
PMC [ PMC-SIERRA, INC ]
