RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
The 64-bit SysAD bus present on the RM7965A processor enables 36 bits of physical
addressing and 64 bits of data, and is supported by an 8-bit parity check bus (SysADC[7:0]) and
a 9-bit command bus (SysCmd[8:0]). In addition, there are ten handshake signals and ten
interrupt inputs. It can run up to 133 MHz in standard LVTTL mode, or up to 200 MHz in the
enhanced HSTL mode. The SysAD bus runs at the same frequency as the RM7965A master
clock. The SysAD interface for the RM7965A also supports up to two outstanding reads, and it
can return the reads out of order.
The SysAD bus is also configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The data rate and the bus frequency at which RM7965A product transmits
data to the system interface is programmable at boot time via mode control bits. Additionally,
the rate at which the processor receives data is fully controlled by the external device.
Therefore, either a low cost interface requiring no read or write buffering, or a faster, high-
performance interface can be designed to communicate with the RM7965A processor.
6.2 System Command Bus
All RM7965A processors feature a 9-bit System Command bus, SysCmd[8:0]. The command
bus indicates whether the SysAD bus carries address or data information on a per-clock basis. If
the SysAD bus carries an address, the SysCmd bus indicates the transaction type (for example,
a read or write). If the SysAD bus carries data, then the SysCmd bus contains information about
the data (for example, this is the last data word transmitted, or the data contains an error). The
SysCmd bus is bidirectional to support both processor requests and external requests to the
RM7965A. Processor requests are initiated by the RM7965A and responded to by an external
device. External requests are issued by an external agent and require the RM7965A to respond.
The RM7965A support 1 to 8-byte transfers as well as 32-byte block transfers on the SysAD
bus. In the case of a sub-doubleword transfer, the 3 low-order address bits give the byte address
of the transfer, and the SysCmd bus indicates the number of bytes being transferred.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
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PMC [ PMC-SIERRA, INC ]
