RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
In the control space, the E9000 supports three new registers to support the 64-entry branch
Trace Buffer: Trace Buffer Control and Status (TB CSR), Trace Buffer Out (TB Out), and Trace
Buffer Index (TB IDX). See Section 7.1
Figure 5 shows the CP0 registers.
Figure 5 CP0 Registers
Context
4*
BadVAddr
8*
Perf Counter
25*
IPLLO
18*
PageMask
5*
EntryLo0
2*
EntryLo1
3*
Count
9*
Compare
11 *
Perf Ctr Cntrl
22*
IPLHI
19*
EntryHi
10*
PRId
15*
47/63
Watch2
19*
Status
12*
Cause
13*
IntControl
20*
Info
7*
Index
0
EPC
14*
Watch1
18*
Watch Mask
21
DErrAddr0
26*
TLB
XContext
20*
EJTAG Debug
23*
DErrAddr1
27*
Random
1
EJTAG DEPC
24*
ECC
26*
CacheErr
27*
Wired
6*
TB CSR
22*
(entries protected
from TLBWR)
Config
16*
ErrorEPC
30*
EJTAG Desave
31*
TB Out
23*
0
TB IDX
24*
LLAddr
17*
TagLo
28*
Ta g H i
29*
Used for memory
management
Used for exception
processing
* Register number
(set1)
4.14 Memory Management Unit (MMU)
The E9000 has an MMU with a 64 entry TLB, with each entry having dual pages for a total of
128 pages. The page size is programmable to be 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 16 MB,
64 MB, or 256 MB. Pages can be programmed to be write-protected. The TLB can operate
statically or in a demand-paged environment, with TLB misses generating exceptions to load
the appropriate page. The TLB replacement algorithm is random, and there is a TLB fence that
can be used to lock a subset of the TLB entries, and allow the remainder to be dynamically
refilled. The MMU architecture on the E9000 supports both 32 and 64-bit virtual addressing.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
23
PMC [ PMC-SIERRA, INC ]
