RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
When the E9000 is configured for 64-bit addressing, the virtual address space layout is an
upward compatible extension of the 32-bit virtual address space layout.
4.16 Joint TLB …
For fast virtual-to-physical address translation, the E9000 uses a large, fully associative TLB
that maps virtual pages to their corresponding physical addresses. As indicated by its name, the
JTLB is used for both instruction and data translations. The JTLB is organized as pairs of
even/odd entries, and maps a virtual address and address space identifier (ASID) into the large,
64 GB physical address space. By default, the JTLB is configured as 48 pairs of even/odd
entries. The optional 64-even/odd-entry configuration is set at boot time.
Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characteristics of various memory regions. First, the page size can be configured,
on a per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in 4x multiples). The CP0
PageMask register is loaded with the desired page size of a mapping, and that size is stored into
the TLB, along with the virtual address, when a new entry is written. Thus, operating systems
can create special purpose maps; for example, an entire frame buffer can be memory mapped
using only one TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
E9000 provides a random replacement algorithm to select a TLB entry to be written with a new
mapping. The core also provides a mechanism whereby a system specific number of mappings
can be locked into the TLB, thereby avoiding random replacement. This mechanism uses the
CP0 Wired register and allows the operating system to guarantee that certain pages are always
mapped for performance reasons and to avoid a deadlock condition. It also facilitates the design
of real-time systems by allowing deterministic access to critical software.
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine whether the coherency algorithm is:
uncached
write-back
write-through with write-allocate
write-through without write-allocate
write-back with secondary and tertiary bypass
Note that both of the write-through protocols bypass both the secondary and the tertiary caches
since neither of these caches support writes of less than a complete cache line.
These protocols are used for both code and data in the E9000, with data using write-back or
write-through depending on the application. The write-through modes support the same efficient
frame buffer handling as the RM7000 and RM5200 Families.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
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