RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Note that integer multiply/divide instructions, as well as their corresponding MFHi and MFLo
instructions, can only be executed in the F pipe execution unit. Within each execution unit, the
operational characteristics are the same as on previous MIPS designs with single cycle ALU
operations (add, sub, logical, shift), one cycle load delay, and an autonomous multiply/divide
unit.
4.6.1
Register File
The E9000 has 32 general-purpose registers with register location 0 (r0) hard wired to a zero
value. These registers are used for scalar integer operations and address calculation. In order to
service the two integer execution units, the register file has four read ports and two write ports
and is fully bypassed both within and between the two execution units to minimize operation
latency in the pipeline.
4.7 Integer ALU
The E9000 has two complete integer ALUs each consisting of an integer adder/subtractor, a
logic unit, and a shifter. Table 4 shows the functions performed by the ALUs for each execution
unit. Each of these units is optimized to perform all operations in a single processor cycle.
Table 4 Integer ALU Operations
Unit
F Pipe
M Pipe
Adder
Logic
Shifter
add, sub
add, sub, data address add
logic, moves, zero shifts (nop)
non-zero shift, store align
logic, moves, zero shifts (nop)
non-zero shift
4.8 Integer Multiply/Divide
The E9000 has a single dedicated integer multiply/divide unit optimized for high-speed multiply
and multiply-accumulate operations. The multiply/divide unit resides in the F pipe execution
unit. Table 5 shows the performance of the multiply/divide unit on each operation.
Table 5 Integer Multiply/Divide Operations
Opcode
Operand Size
16 bit
Latency
Repeat Rate
Stall Cycles
MULT/U, MAD/U
4
3
0
0
2
3
0
0
0
32 bit
5
4
MUL
16 bit
4
3
32 bit
5
4
DMULT, DMULTU any
9
8
DIV, DIVD
any
any
36
68
36
68
DDIV, DDIVU
MSUB, MSUBU
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