RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
4.11 Floating-Point General Register File
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions, LDC1 and SDC1, the floating-point unit can
take advantage of the 64-bit wide data cache and issue a floating-point coprocessor load or store
doubleword instruction in every cycle.
The floating-point control register file contains two registers; one for determining configuration
and revision information for the coprocessor, and one for control and status information. These
registers are primarily used for diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
To support superscalar operations the FGR has four read ports and two write ports and is fully
bypassed to minimize operation latency in the pipeline. Three of the read ports and one write
port are used to support the combined multiply-add instruction while the fourth read and second
write port allows for concurrent floating-point load or store and conditional move operations.
4.12 System Control Coprocessor (CP0)
The system control coprocessor (CP0) is responsible for the virtual memory sub-system, the
exception control system, and the diagnostics capability of the processor.
For memory management support, the E9000 CP0 is logically identical to the CPU cores used
in the RM5200 Family and the RM7000 Family. For interrupt exceptions and diagnostics, the
E9000 is a superset of the RM5200 Family and the RM7000 Family, implementing additional
features described in the following sections on Interrupts, Test/ Breakpoint registers, and
Performance Counters.
The memory management unit controls the virtual memory system page mapping. It consists of
an instruction address translation buffer (ITLB) a data address translation buffer (DTLB), a
Joint TLB (JTLB), and coprocessor registers used by the virtual memory mapping sub-system.
4.13 System Control Coprocessor Registers
The E9000 incorporates all CP0 registers internally. These registers provide the path through
which the virtual memory system’s page mapping is examined and modified, exceptions are
handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or
disabled, cache features). In addition, the E9000 includes registers to implement a real-time
cycle counting facility, to aid in cache and system diagnostics, and to assist in data error
detection.
To support the non-blocking caches and enhanced interrupt handling capabilities of the E9000,
both the data and control register spaces of CP0 are supported. In the data register space, which
is accessed using the MFC0 and MTC0 instructions, the E9000 supports the same registers as
found in previous RM7000 processors plus three new registers to support EJTAG Debugging.
The three new registers are called: EJTAG Debug, EJTAG DEPC, and EJTAG DESave.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
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PMC [ PMC-SIERRA, INC ]
