RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
4.17 Instruction TLB
The E9000 uses a 4-entry instruction TLB (ITLB). The ITLB offers the following advantages:
Minimizes contention for the JTLB
Eliminates the critical path of translating through a large associative array
Allows instruction address and data address translations to occur in parallel
Saves power
Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction
address translation to occur in parallel with data address translation. When a miss occurs on an
instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the
JTLB. The operation of the ITLB is completely transparent to the user.
4.18 Data TLB …
The E9000 uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB.
Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data
address translation to occur in parallel with instruction address translation. When a miss occurs
on a data address translation, the DTLB is filled from the JTLB. The DTLB refill is pseudo-
LRU; the least recently used entry of the least recently used pair of entries is filled. The
operation of the DTLB is completely transparent to the user.
4.19 Interrupt Handling
In order to provide better real time interrupt handling, the RM7965A provides 10 external
hardware interrupts, each of which can be separately prioritized and separately vectored.
The performance counter is also a hardware interrupt source using INT13. Historically in the
MIPS architecture, interrupt 7 (INT7) was used as the Timer Interrupt. The RM7965A provides
a separate interrupt, INT12, for this purpose, thereby releasing INT7 for use as a pure external
interrupt.
All interrupts (INT[13:0]), the Performance Counter, and the Timer, have corresponding
interrupt mask bits, IM[13:0], and interrupt pending bits, IP[13:0], in the Status, Interrupt
Control, and Cause registers. The bit assignments for the Interrupt Control and Cause registers
are shown in Table 8 and Table 9. (Note the Status register has not changed from the RM5200
product family and is not shown.)
Table 8 Cause Register
31
30
29:28 27
26
25
24
23:8
7
6:2
0:1
BD
0
CE
0
W2
W1
IV
IP[15:0]
0
EXC
0
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
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PMC [ PMC-SIERRA, INC ]
