RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Table 9 Interrupt Control Register
31:16
15:8
7
6:5
4:0
0
IM[15:8]
TE
0
Spacing
The IV bit in the Cause register is the global enable bit for the enhanced interrupt features. If
this bit is clear then interrupt operation is compatible with RM5200 and RM7000 products.
In the Interrupt Control register, the interrupt vector spacing is controlled by the Spacing field
as described below. The Interrupt Mask field (IM[13:8]) contains the interrupt mask for
interrupts 8 through 13. IM[15:14] are reserved for future use.
The Timer Enable (TE) bit is used to gate the Timer Interrupt to the Cause Register. If TE is set
to 0, the Timer Interrupt is not gated to IP12. If TE is set to 1, the Timer Interrupt is gated to
IP12.
The setting for Mode Bit 11 is used to determine if the Timer Interrupt replaces the external
interrupt (INT5*) as an input to IP7 in the Cause Register. If Mode Bit 11 is set to 0, the Timer
Interrupt is gated to IP7. If Mode Bit 11 is set to 1, the external INT5* is gated to IP7.
In order to utilize both the external Interrupt (INT5*) and the internal Timer Interrupt, Mode Bit
11 must be set to 1, and TE must be set to 1. In this case, the Timer Interrupt will utilize IP12,
and INT5* will utilize IP7. Please also reference the logic diagram for interrupt signals in the
RM7965A User Manual.
The Interrupt Control register uses IM13 to enable the Performance Counter interrupt and to
enable the Trace Buffer interrupt.
Priority of the interrupts is set via two new coprocessor 0 registers called Interrupt Priority
Level Lo (IPLLO) and Interrupt Priority Level Hi (IPLHI).
In the IPLLO and IPLHI registers, each interrupt is represented by a four-bit field, thereby
allowing each interrupt to be programmed with a priority level from 0 to 15 inclusive. The
priorities can be set in any manner, including having all the priorities set exactly the same.
Priority 0 is the highest level and priority 15 the lowest. The format of the priority level
registers is shown in Table 10 and Table 11. The priority level registers are located in the
coprocessor 0 control register space.
Table 10 IPLLO Register
31:28 27:24 23:20 19:16 15:12 11:8
7:4
3:0
IPL7
IPL6
IPL5
IPL4
IPL3
IPL2
IPL1
IPL0
Table 11 IPLHI Register
31:28 27:24 23:20 19:16 15:12 11:8
7:4
3:0
0
0
IPL13
IPL12
IPL11
IPL10
IPL9
IPL8
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
27
PMC [ PMC-SIERRA, INC ]
