RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed
in the Hi and Lo registers. These values can then be transferred to the general-purpose register
file using the Move-from-Hi and Move-from-Lo (MFHI/MFLO) instructions.
In addition to the baseline MIPS IV integer multiply instructions, the E9000 also implements
the 3-operand multiply instruction, MUL. This instruction specifies that the multiply result go
directly to the integer register file rather than the Lo register. The portion of the multiply that
would have normally gone into the Hi register is discarded. For applications where it is known
that the upper half of the multiply result is not required, using the MUL instruction eliminates
the necessity of executing an explicit MFLO instruction.
The multiply-add instructions, MAD and MADU, multiply two operands and add the resulting
product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is
the core primitive of almost all digital signal processing algorithms. Therefore, using the E9000
eliminates the need for a separate DSP in many embedded applications.
The multiply-sub instructions, MSUB and MSUBU, multiply two operands and subtract the
resulting product from the current contents of the Hi and Lo registers. The multiply-subtract
operation is a core primitive of digital signal processing algorithms.
4.9 Floating-Point Coprocessor
The E9000 incorporates a high-performance fully pipelined floating-point coprocessor that
includes a floating-point register file and autonomous execution units for multiply/add/convert
and divide/square root. The floating-point coprocessor is a tightly coupled execution unit,
decoding and executing instructions in parallel with, and in the case of floating-point loads and
stores, in cooperation with the M pipe of the integer unit. The superscalar capabilities of the
E9000 allow floating-point computation instructions to issue concurrently with integer
instructions.
4.10 Floating-Point Unit
The E9000 floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square
root unit and a pipelined multiply/add unit. Overlap of divide/square root and multiply/add is
supported.
The E9000 maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
Floating-point operations include:
add
subtract
multiply
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