RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
4.3.2
E9000 Pipeline Stages
In contrast to the RM7000 pipeline, the E9000 pipeline has two additional stages to allow an
extra clock cycle of for both the instruction and the data pipeline regimes. The E9000 pipeline
stages can be summarized as follows:
I: Instruction Addressing
C: Instruction Cache Access
R: Register File Access, Instruction Decode
A: Instruction Execution, Data Address Calculation
D: Data Cache Access
M: Data Bus, Data Alignment
W: Write Back to register file
The pipeline execution diagram for the E9000 is shown below:
Figure 4 Pipeline Execution Diagram
M-Pipe
Simple Integer Unit
with L/S Unit
A
D
M
Fetch and Dispatch
(2 instructions per cycle)
W
W
Integer MAC Unit
MAC1 MAC2 MAC3
I
C
C
R
R
F-Pipe
Simple Integer Unit
I
A
D
M
Floating-point MAC Unit
F2 F3 F4
F1
F5
Floating-point Div/Sqrt Unit
(Iterative)
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
17
PMC [ PMC-SIERRA, INC ]
