RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Table 3 Dual Issue Instruction Classes
Integer ALU
Load/Store
Floating- Point
Branch
Integer Mul/Div
add, sub, or, xor,
shift, etc.
lw, sw, ld, sd,
ldc1, sdc1, mov,
movc, fmov, etc.
fadd, fsub, fmult,
fmadd, fdiv, fcmp,
fsqrt, etc.
beq, bne, bCzT,
bCzF, j, etc.
mult, multu, mad,
madu, mul, dmult,
dmultu, div, divd,
ddiv, ddivd
4.3 Seven-stage Pipeline
The E9000 pipeline has been increased to 7 stages versus the 5-stage RM7000 pipeline.
Increasing the pipeline to 7 stages and including branch prediction allows the frequency to be
increased beyond 800 MHz while maintaining high pipeline efficiency. Figure 3 illustrates the
7-stage pipeline in comparison to the 5-stage pipeline of the RM7000.
Figure 3 Pipeline Comparison
RM7000 Pipeline
I
R
A
D
W
W
I
C
R
A
D
M
E9000 Pipeline
4.3.1
RM7000 Pipeline Stages
The RM7000 pipeline stages are summarized as follows:
I: Instruction Fetch from instruction cache
R: Register File Access
A: Instruction Execution
D: Data Fetch from data cache
W: Write Back to register file
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
16
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