RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
4.2 Superscalar Dispatch
The E9000 incorporates a superscalar dispatch unit that allows it to issue up to two instructions
per cycle. For purposes of instruction issue, the E9000 defines four classes of instructions:
integer, load/store, branches, and floating-point. There are two logical pipelines, the function, or
F, pipeline and the memory, or M, pipeline. Note that the M pipe can execute integer as well as
memory type instructions.
Table 2 Instruction Issue Rules
F Pipe
M Pipe
one of:
one of:
Integer ALU, branch, floating-point, integer mul, div
Integer ALU, load/store
Figure 3 is a simplification of the execution unit, and illustrates the basics of the instruction
issue mechanism.
Figure 3 Instruction Issue Paradigm
Instruction
Cache
Dispatch
Unit
F Pipe IBus
M Pipe IBus
FP
F Pipe
FP
M Pipe
Integer
M Pipe
Integer
F Pipe
The figure illustrates that one F pipe instruction and one M pipe instruction can be issued
concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 3 specifies
more completely the instructions within each class.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
15
PMC [ PMC-SIERRA, INC ]
