RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
4
E9000 CPU Core
The RM7965A product consists of the E9000 core plus system interface logic. The E9000 is
compatible with the MIPS64 instruction set architecture (ISA), which is a superset of the MIPS
IV ISA and is fully backwards compatible with the RM7000 CPU core utilized in all RM70xx
products. Also included in the E9000 core is a high performance, IEEE 754 compliant floating-
point unit.
The E9000 core includes a dual-integer superscalar processor with a two level cache hierarchy,
an MMU, and a sophisticated branch predictor. Support is provided for two outstanding reads
with out-of-order return. The interrupt controller works in conjunction with the system interrupt
controller to provide a robust interrupt architecture.
The E9000 core also contains an integrated EJTAG debug module and an integrated Test Access
Port (TAP) controller, both of which allow easy debug from the JTAG interface. A 64-entry
pipeline-rate trace buffer is included for real-time program flow analysis.
4.1 CPU Registers
The E9000 contains 32 general purpose registers (GPR), two special purpose registers for
integer multiplication and division, and a program counter; there are no condition code bits.
Figure 2 shows these processor registers. The E9000 also includes two sets of CP0 registers.
The CP0 register sets contain both 32 and 64-bit registers. Only 29 of the 32 registers specified
in CP0 Set 0 are implemented, and only 5 of the 32 registers in CP0 Set 1 are implemented.
Figure 2 General Purpose Registers
63
0
Multiply/Divide Registers
r0
r1
63
63
0
0
HI
r2
*
LO
Program Counter
PC
*
*
R29
R30
R31
63
0
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
14
PMC [ PMC-SIERRA, INC ]
