Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 52. Control Packet Exchange Between Linecard CPU and ETT1 CPU
Portcard
Linecard
Dataslice (6 of)
Fiber Link
CPU
OOB
PP
Satellite
OOB
Controller
TT1 CPU
The linecard can send a Control packet to the portcard (once the fiber link is operational). This Control
packet is stored in a special input queue that can store up to eight of these packets. Once the packet is
stored the EPP can issue an interrupt to the ETT1 CPU indicating the arrival of a Control packet. The ETT1
CPU can then read the Control packet directly from the Dataslice memory.
NOTE: The ingress Control packet queue is eight cells deep and there is no flow control imposed
on the Control packets sent from the linecard - if the linecard sends control packets faster
than the ETT1 CPU can read them then Control packets will be lost. Some form of reliable
flow control should be handled between the two CPUs.
In the egress direction, the ETT1 CPU can create a Control packet within the Dataslice memory. Once
created the CPU issues a write command to the EPP and the cell will be transmitted to the linecard.
This mechanism allows the ETT1 CPU to communicate directly with the linecard. This also tests the fiber
link, although at a limited cell rate.
1.12.3.3 Testing Error Detection Logic
The ETT1 CPU can send any arbitrary cell to the linecard CPU. The ETT1 CPU simply writes the entire cell
into the Dataslice memory, then instructs the EPP to send it by writing to the EPP’s “Output UC Queue
112
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
