Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 51. Loopback Path
Portcard
Linecard
Dataslice (6 of)
Fiber Link
CPU
OOB
Satellite
EPP
OOB
Controller
ETT1 CPU
The loopback function is controlled from the portcard, and so the linecard must have some form of
out-of-band communication in order to set either the Serdes or Dataslice into loopback mode.
NOTE: While the Dataslice is in loopback, the ingress cells are still received and passed to the
EPP. The EPP should be disabled to prevent it from attempting to forward the incoming
cells while the portcard is in loopback mode. Also, the EPP must be programmed to send
only idle cells. (Set the EIDLCT register to 0x0.)
NOTE: If a Mux device is used then the mux bits in the LCS header should be set correctly so as
to be returned to the correct OC-48c port. These mux bits will not be modified when the
portcard is in loopback mode, and thus must be set correctly for both ingress and egress
directions.
Some Serdes parts can be set to loopback at their serial outputs - so that the egress cells can be looped
back to the ingress direction of the portcard. A portcard could use this feature to test the Serdes logic
without needing a linecard to be attached.
1.12.3.2 Establishing Linecard to ETT1 Communication.
The LCS protocol provides support for Control packets which can be exchanged between the linecard
CPU and the ETT1 CPU. Figure 52 shows the flow of cells between CPUs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
111
PMC [ PMC-SIERRA, INC ]
