Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 54. Dataslice Data Flow
AIB
oQM
8B/10B
oBypass
oFIFO
Encoder
8B/10B
CR
AIB
iBypass
iFIFO
iQM
Decoder
core clocks
PLL
OOB Interface
JTAG
Control/Status Registers
The iFIFO is an eight-cell-deep and the oFIFO is a four-cell-deep FIFO that perform clock decoupling
functions between the port card and the linecard and provide buffering between the queue memory and
the outside world.
The iBypass and oBypass registers are temporary storage areas; eight-cell-deep FIFOs that provide the
cell bypass function of the Dataslice. When a cell arrives from the Linecard, nine of the 12 Dataslices store
the cell temporarily in their iBypass register. The three remaining Dataslices send their portion of the cell to
the EPP. The EPP instructs the Dataslices to transfer the cell from the iBypass register to a specific input
queue. The same general flow occurs for the oBypass, except that all 12 Dataslices use the oBypass.
There is a constant, programmable depth for each of the bypass registers. This depth is set during
initialization through the Out-Of-Band (OOB) bus by the CPU.
The iQM and oQM are the on-device queue memories used for storing cells in the input queues and output
queues, respectively. The iQM and oQM queue memories are each 8,704 cells deep and 48 bits wide.
116
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
