Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
2
Dataslice
This chapter contains information on the Dataslice device, part number PM9313-HC, available from
PMC-Sierra, Inc.
The Dataslice contains queue storage for all cells that have arrived at the input port from the linecard and
all cells that have passed through the Crossbar to the output port before departing to the linecard. The
Dataslice interfaces to the linecards with 8B/10B encoded physical links, operating at 1.5 Gbit/s. Each
Dataslice device packages two independent logical Dataslice units. The ingress and egress datapath is
striped between Dataslices such that the first six bytes of the LCS cell are sent through logical Dataslice 0;
the next six bytes through logical Dataslice 1, etc. Six Dataslice devices are required on each port card in
order to process 72-byte LCS cells. An alternative configuration uses seven Dataslice devices to process
84-byte LCS cells, carrying a 76-byte payload.
2.1 DATASLICE BLOCKS
The following discussion assumes 12 logical Dataslices per port. (6 devices).
There are 12 logical Dataslice units, packaged in six ICs, on a 72-byte LCS cell port card. Each logical
Dataslice unit has a full-duplex, 10-bit wide, parallel bus connection to a Serdes device on the linecard
interface, two bidirectional AIB connections to two Crossbars, two 8-bit busses for data from the ingress
and egress paths to the Enhanced Port Processor, one bus for processed ingress data from the EPP, and
two unidirectional 8-bit busses for ingress and egress control information from the EPP.
Figure 54 shows how cells flow through the Dataslice.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
115
PMC [ PMC-SIERRA, INC ]
