Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
1.12 ETT1 DIAGNOSTICS
An ETT1-based switch is a highly sophisticated system which is typically required to demonstrate very high
levels of uptime. In order to achieve this uptime it is important to be able to:
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•
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Ensure that a subsystem is operating correctly before it is brought online.
Identify subsystems that have failed as quickly as possible.
Diagnose failures to determine the specific entity that should be replaced.
This document describes a number of diagnostics that customers might find useful in addressing these
needs.
The following terminology is used to describe a subsystem within a switch:
offline: the subsystem is not interacting with the rest of the system except via the OOB bus. AIB links may
be taken up and down but will not cause changes to other subsystems.
online, inactive:the subsystem may be receiving signals from the system, and may be sending cells to
itself, thus contending for fabric bandwidth. It only sends/receives diagnostic cells, not customer traffic.
online, active:the subsystem is participating in the normal operation of the switch, sending and receiving
customer traffic and maintenance/diagnostic cells.
1.12.1 Device Tests
All of the ETT1 devices have a number of registers. The local ETT1 CPU can read from and write to many
of these registers. Some care must be taken when modifying the contents of registers as they may have
side effects that will affect the operation or cell flow of system components that are already online and
active. In general, configuration registers should not be modified once a subsystem is online and active.
The CPU can read most registers at any time without effect, however some registers, particularly interrupt
registers and statistics counters, are cleared when they are read.
Some of the ETT1 devices contain memory structures (RAMs). Many of these RAMs can be written to and
read from by the local CPU. Since the internal BIST mechanism is not available to the CPU, it is
recommended that a customer verify the correct operation of such memory structures by a soak test in
which the CPU writes and reads to all locations. Such a test should perform the widely known test patterns
such as walking 1’s, 0’s, checkerboard, etc. Of course these tests are destructive to the current contents
and can only be performed on RAMs that are not being used. In practice very few of the RAMs can be
modified once the devices are active. The RAMs can be read non-destructively, and a great deal of internal
system information is available this way; however unless the exact state of the system is known at the
instance the RAM is read, then it is difficult to know if the returned value is correct. Obviously, RAMs that
implement TDM and multicast tables are designed to be modified with due care during normal operation.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
