PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
Type
Input
Pin
No.
Function
TXDATA[0]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
TXDATA[8]
TXDATA[9]
TXDATA[10]
TXDATA[11]
TXDATA[12]
TXDATA[13]
TXDATA[14]
TXDATA[15]
R24
R25
R26
P24
P25
N24
N23
M26
L25
K26
L24
K25
L23
J26
K24
J25
The transmit data signals (TXDATA[15:0])
contain the transmit Any-PHY packet interface
(APPI) data provided by the external controller.
Data must be presented in big endian order, i.e.
the byte in TXDATA[15:8] is transmitted by the
FREEDM-84A672 before the byte in
TXDATA[7:0].
The first word of each data transfer contains an
address to identify the device and channel
associated with the data being transferred. This
prepended address must be qualified with the
TSX signal. The 10 least significant bits provide
the channel number (0 to 671) while the 3 most
significant bits select one of seven possible
FREEDM-84A672 devices sharing a single
external controller. (One address is reserved as
a null address.) The FREEDM-84A672 will not
respond to channel addresses outside the range
0 to 671, nor to device addresses other than the
base address stored in the TAPI672 Control
register.
The second and any subsequent words of each
data transfer contain packet data.
The TXDATA[15:0] signals are sampled on the
rising edge of TXCLK.
TXPRTY
Input
M23
The transmit parity signal (TXPRTY) reflects the
odd parity calculated over the TXDATA[15:0]
signals. TXPRTY is only valid when
TXDATA[15:0] are valid.
TXPRTY is sampled on the rising edge of
TXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
21
PMC [ PMC-SIERRA, INC ]
