RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Pin
No.
Function
TERR
Input
P1
The transmit error signal (TERR) indicates that
the current packet is errored and should be
aborted. TERR is only valid when TEOP is
sampled high. When TERR is sampled high
and TEOP is sampled high, the current packet is
errored and the FREEDM-32A256 will respond
accordingly. When TERR is sampled low and
TEOP is sampled high, the current packet is not
errored. TERR must be set low when TEOP is
set low.
TERR is sampled on the rising edge of TXCLK.
RXCLK
Input
Input
AC2
The receive clock signal (RXCLK) provides
timing for the receive Any-PHY packet interface
(APPI). RXCLK is a nominally 50% duty cycle,
25 to 50 MHz clock.
The receive address signals (RXADDR[2:0])
serve two functions – device polling and device
selection. When polling, the RXADDR[2:0]
signals provide an address for polling a
FREEDM-32A256 device for receive data
available in any one of its 256 channels. Polling
results are returned on the RPA tristate output.
During selection, the address on the
RXADDR[0]
RXADDR[1]
RXADDR[2]
AC3
Y4
AB2
RXADDR[2:0] signals is qualified with the RENB
signal to select a FREEDM-32A256 device
enabling it to output data on the receive APPI.
Note that up to seven FREEDM-32A256
devices may share a single external controller
(one address is reserved as a null address).
The Rx APPI of each FREEDM-32A256 device
is identified by the base address in the RAPI256
Control register.
The RXADDR[2:0] signals are sampled on the
rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL
28
PMC [ PMC-SIERRA, INC ]
