RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Input
Pin
No.
Function
TXDATA[0]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
TXDATA[8]
TXDATA[9]
TXDATA[10]
TXDATA[11]
TXDATA[12]
TXDATA[13]
TXDATA[14]
TXDATA[15]
N4
N1
N3
N2
M2
M3
L3
L2
K3
K2
K1
J3
The transmit data signals (TXDATA[15:0])
contain the transmit Any-PHY packet interface
(APPI) data provided by the external controller.
Data must be presented in big endian order, i.e.
the byte in TXDATA[15:8] is transmitted by the
FREEDM-32A256 before the byte in
TXDATA[7:0].
The first word of each data transfer contains an
address to identify the device and channel
associated with the data being transferred. This
prepended address must be qualified with the
TSX signal. The 8 least significant bits provide
the channel number (0 to 255) while the 3 most
significant bits select one of seven possible
FREEDM-32A256 devices sharing a single
external controller. (One address is reserved as
a null address.) The FREEDM-32A256 will not
respond to channel addresses outside the range
0 to 255, nor to device addresses other than the
base address stored in the TAPI256 Control
register.
J2
J4
J1
H3
The second and any subsequent words of each
data transfer contain packet data.
The TXDATA[15:0] signals are sampled on the
rising edge of TXCLK.
TXPRTY
Input
L4
The transmit parity signal (TXPRTY) reflects the
odd parity calculated over the TXDATA[15:0]
signals. TXPRTY is only valid when
TXDATA[15:0] are valid.
TXPRTY is sampled on the rising edge of
TXCLK.
PROPRIETARY AND CONFIDENTIAL
26
PMC [ PMC-SIERRA, INC ]
