RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Pin
No.
Function
TPA1[0]
TPA1[1]
TPA1[2]
TPA2[0]
TPA2[1]
TPA2[2]
Tristate D3
The transmit packet available signals (TPA1[2:0]
and TPA2[2:0]) reflects the status of a poll of
two transmit channel FIFOs. TPA1[2:0] returns
the polled results for channel address ‘n’
Output
C1
D4
B2
B1
A1
provided on TXADDR[12:0] and TPA2[2:0]
returns the polled results for channel address
‘n+1’. TPAn[2] reports packet underrun events
and TPAn[1:0] report the fill state of the transmit
channel FIFO. TPAn[2] is set high when one or
more packets has underrun on the channel and
a further data transfer has occurred since it was
last polled. When TPAn[2] is set low, no packet
has underrun on the channel since the last poll.
TPAn[1:0] are coded as follows:
TPAn[1:0] = “11” => Starving
TPAn[1:0] = “10” => (Reserved)
TPAn[1:0] = “01” => Space
TPAn[1:0] = “00” => Full
A “Starving” polled response indicates that the
polled transmit channel FIFO is at risk of
underflowing and should be supplied with data
as soon as possible. A “Space” polled response
indicates that the polled transmit channel FIFO
can accept XFER[3:0] plus one blocks (16 bytes
per block) of data. A “Full” polled response
indicates that the polled transmit channel FIFO
cannot accept XFER[3:0] plus one blocks of
data. (XFER[3:0] is a per-channel
programmable value – see description of
register 0x38C.)
It is the responsibility of the external controller to
prevent channel underflow conditions by
adequately polling each channel before data
transfer.
TPAn[2:0] are tristate during reset and when a
device address other than the FREEDM-
32A256’s base address is provided on
TXADDR[12:10].
PROPRIETARY AND CONFIDENTIAL
24
PMC [ PMC-SIERRA, INC ]
