RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Pin
No.
Function
RXDATA[0]
RXDATA[1]
RXDATA[2]
RXDATA[3]
RXDATA[4]
RXDATA[5]
RXDATA[6]
RXDATA[7]
RXDATA[8]
RXDATA[9]
RXDATA[10]
RXDATA[11]
RXDATA[12]
RXDATA[13]
RXDATA[14]
RXDATA[15]
Tristate AC1
The receive data signals (RXDATA[15:0])
contain the receive Any-PHY packet interface
(APPI) data output by the FREEDM-32A256
when selected. Data is presented in big endian
format, i.e. the byte in RXDATA[15:8] was
received by the FREEDM-32A256 before the
byte in RXDATA[7:0].
The first word of each data transfer (when RSX
is high) contains an address to identify the
device and channel associated with the data
being transferred. The 8 least significant bits
(RXDATA[7:0]) contain the channel number (0 to
255) and the 3 most significant bits
Output
AB1
AA3
AA1
AA2
Y3
W4
Y1
W3
W1
V3
V1
V2
U1
(RXDATA[15:13]) contain the device base
address. The second and any subsequent
words of each data transfer contain valid data.
The FREEDM-32A256 may be programmed to
overwrite RXDATA[7:0] of the final word of each
packet transfer (REOP is high) with the status of
packet reception when that packet is errored
(RERR is high). This status information is bit
mapped as follows:
U4
U2
RXDATA[0]=’1’ => channel FIFO overrun.
RXDATA[1]=’1’ => max. packet length violation.
RXDATA[2]=’1’ => FCS error.
RXDATA[3]=’1’ => non-octet aligned.
RXDATA[4]=’1’ => HDLC packet abort.
RXDATA[7:5]=”Xh” => Reserved.
The RXDATA[15:0] signals are tristate when the
FREEDM-32A256 device is not selected via the
RENB signal.
The RXDATA[15:0] signals are updated on the
rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL
31
PMC [ PMC-SIERRA, INC ]
