RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Pin
No.
Function
RXPRTY
RSX
Tristate U3
The receive parity signal (RXPRTY) reflects the
odd parity calculated over the RXDATA[15:0]
signals. RXPRTY is driven/tristate at the same
time as RXDATA[15:0].
Output
RXPRTY is updated on the rising edge of
RXCLK.
Tristate Y2
Output
The receive start of transfer signal (RSX)
denotes the start of data transfer on the receive
APPI. When the RSX signal is set high, the 3
most significant bits on the RXDATA[15:0]
signals contain the FREEDM-32A256 device
address and the 10 least significant bits on the
RXDATA[15:0] signals contain the channel
address associated with the data to follow. Valid
device addresses are in the range 0 through 7
(with one address reserved as a null address)
and valid channel addresses are in the range 0
through 255. When the RSX signal is sampled
low, the word on the RXDATA[15:0] signals does
not contain a device and channel address.
RSX is tristate when the FREEDM-32A256
device is not selected via the RENB signal.
RSX is updated on the rising edge of RXCLK.
It is recommended that RSX be connected
externally to a weak pull-down, e.g. 10 kꢂ.
REOP
Tristate T3
Output
The receive end of packet signal (REOP)
denotes the end of a packet. REOP is only valid
during data transfer. When REOP is set high,
RXDATA[15:0] contains the last data byte of a
packet. When REOP is set low, RXDATA[15:0]
does not contain the last data byte of a packet.
REOP is tristate when the FREEDM-32A256
device is not selected via the RENB signal.
REOP is updated on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL
32
PMC [ PMC-SIERRA, INC ]
