S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Pin Name Type
Pin
No.
Function
The Cell Buffer SDRAM Address (CBA[10:0]) signals identify the
row address (CBA[10:0]) and column address (CBA[7:0]) for the
locations accessed.
CBA[10]
CBA[9]
CBA[8]
CBA[7]
CBA[6]
CBA[5]
CBA[4]
CBA[3]
CBA[2]
CBA[1]
CBA[0]
Output W7
Y9
AA9
AB9
The CBA[10:0] output is updated on the rising edge of SYSCLK.
W9
Y10
AA10
AB10
W10
AB11
W11
The Cell Buffer SDRAM Bank Select (CBBS) signals determine
which bank of a dual/quad bank Cell Buffer SDRAM chip is active.
CBBS is generated along with the row address when CBRASB is
asserted low.
CBBS
Output AA12
The CBBS outputs are updated on the rising edge of SYSCLK.
The Cell Buffer SDRAM Input/Output Data Mask (CBDQM) signal
is held high until the SDRAM initialization is complete and then set
low for normal operation.
CBDQM
Output Y12
The CBDQM output is updated on the rising edge of SYSCLK.
The Cell Buffer SDRAM Data (CBDQ[15:0]) signals interface
CBDQ[15]
CBDQ[14]
CBDQ[13]
CBDQ[12]
CBDQ[11]
CBDQ[10]
CBDQ[9]
CBDQ[8]
CBDQ[7]
CBDQ[6]
CBDQ[5]
CBDQ[4]
CBDQ[3]
CBDQ[2]
CBDQ[1]
CBDQ[0]
I/O
W13
AB13
AA13
Y13
directly with the Cell Buffer SDRAM data ports.
The CBDQ[15:0] bi-directional signals are sampled and
updated/tristated on the rising edge of SYSCLK.
W14
AB14
AA14
W15
AA15
Y15
AB16
AA16
Y16
W18
AA17
AB18
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
37
PMC [ PMC-SIERRA, INC ]
