S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
9.4 Transmit Slave Interface (UTOPIA L2 mode) (26 Signals)
Pin Name Type
Pin
Function
No.
The Transmit Clock (TCLK) signal is used to transfer cells across
TCLK
Input
E19
the ANY-PHY interface to the internal downstream cell buffers.
The TCA output is updated on the rising edge of TCLK.
The TENB, TSOC, TDAT[15:0], TPRTY, TADR[4:0] inputs are
sampled on the rising edge of TCLK.
The TCLK input must cycle at a 52 MHz or lower instantaneous rate.
The Transmit Cell Available (TCA) is an active high signal that
indicates the availability of space in the selected logical channel
FIFO when polled using the TADR[4:0] signals.
TCA
Tristate
Output
L22
The S/UNI-IMA-4 drives TCA with the cell space availability status
for the polled port on TCLK cycles after a valid TADR[4:0] address is
sampled.
The TCA output is high-impedance when not polled.
The TCA output is updated on the rising edge of TCLK.
The Transmit enable bar (TENB) is an active low signal that is
TENB
Input
Input
L20
used to indicate cell transfers to the internal cell buffers.
The TENB input is sampled on the rising edge of TCLK.
The Transmit Address (TADR[4:0]) signals are used to address
TADR[4]
TADR[3]
TADR[2]
TADR[1]
TADR[0]
K21
K20
J19
J22
J21
logical channels for the purposes of polling and device selection.
The TADR[4:0] input bus is sampled on the rising edge of TCLK.
The Transmit Start of Cell (TSOC) is an active high signal that
TSOC
Input
Input
H19
marks the first word of the cell on the TDAT[15:0] bus.
The TSOC input is sampled on the rising edge of TCLK.
The Transmit Cell Data (TDAT[15:0]) signals carry the ATM cell
octets that are transferred to the internal cell buffer. The TDAT[15:0]
signals are considered valid only when the TENB signal is asserted
low. When this interface is operating in 8-bit mode, only TDAT[7:0]
is used.
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
H21
H20
F19
G22
G21
F22
G20
F21
E22
C20
E21
C22
E20
D21
C21
B22
The TDAT[15:0] input bus is sampled on the rising edge of TCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
34
PMC [ PMC-SIERRA, INC ]
