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PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
9.7 Clk/Data (33 signals)  
Pin Name  
Type  
Pin  
Function  
No.  
The Transmit Serial Clock (TSCLK[3:0]) signals contain the  
transmit clocks for the 4 independently timed links. The  
TSDATA[3:0] signals are updated on the falling edge of the  
corresponding TSCLK[3:0] clock.  
TSCLK[3]  
TSCLK[2]  
TSCLK[1]  
TSCLK[0]  
Input  
G1  
F4  
H1  
H3  
For channelized T1 or E1 links, TSCLK[n] must be gapped during  
the framing bit (for T1 interfaces) or during time-slot 0 (for E1  
interfaces) of the TSDATA[n] stream. The S/UNI-IMA-4 uses the  
gapping information to determine the time-slot alignment in the  
transmit stream.  
For unchannelized links, TSCLK[n] must be externally gapped  
during the bits or time-slots that are not part of the transmission  
format payload (i.e., not part of the ATM Cell).  
The TSCLK[3:0] input signal is nominally a 50% duty cycle clock of  
1.544 MHz for T1 links and 2.048 MHz for E1 links.  
The TSCLK[3:0] may operate at higher rates in the unchannelized  
mode. At higher rates, the amount of lines available is limited. See  
section 13.3.1 for more details.  
The Transmit Serial Data (TSDATA[3:0]) signals contain the  
transmit data for the 4 independently timed links. For channelized  
links, TSDATA[n] contains the 24 (T1) or 31 (E1) time-slots that  
comprise the channelized link. TSCLK[n] must be gapped during the  
T1 framing bit position or the E1 frame alignment signal (time-slot  
0). The S/UNI-IMA-4 uses the location of the gap to determine the  
channel alignment on TSDATA[n].  
TSDATA[3]  
TSDATA[2]  
TSDATA[1]  
TSDATA[0]  
Output  
J4  
K2  
K1  
K4  
For unchannelized links, TSDATA[n] contains the ATM cell data. For  
certain transmission formats, TSDATA[n] may contain place holder  
bits or time-slots. TSCLK[n] must be externally gapped during the  
placeholder positions in the TSDATA[n] stream.  
The TSDATA[3:0] output signals are updated on the falling edge of  
the corresponding TSCLK[3:0] clock, or on the falling edge of the  
CTSCLK when the CTSCLK_SEL is set.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
38  
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