S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Pin Name Type
Pin
No.
Function
The Transmit Address (TADR[6:0]) signals are used to address
logical channels for the purpose of polling and device selection. The
TADR[6:0] signals are valid only when the TCSB signal is sampled
active in the following TCLK cycle.
TADR[6]
TADR[5]
TADR[4]
TADR[3]
TADR[2]
TADR[1]
TADR[0]
Input
K19
K22
K21
K20
J19
J22
J21
The TADR[6:0] input bus is sampled on the rising edge of TCLK.
The Transmit Chip Select (TCSB) is an active low signal that is
used to select the S/UNI-IMA-4 transmit interface. When the TCSB
is sampled low, it indicates that the TADR[6:0] sampled at the
previous clock is a valid address. If the TCSB is sampled high, the
device is not selected and the TADR[6:0] sampled on the previous
cycle is not a valid address and is ignored. When sufficient address
space is provided by TADR[6:0] for all devices on the bus, this
signal may be tied low.
TCSB
Input
J20
The TCSB is asserted low one cycle after a valid address is present
on the TADR[6:0] signals.
The TCSB input is sampled on the rising edge of TCLK.
The Transmit Start of Packet (TSOP) is an active high signal that
marks the start of the cell on the TDAT[15:0] bus. When TSOP is
active, the first word of the cell is present on the TDAT[15:0] bus.
TSOP
TSX
Input
Input
H19
H22
The TSOP output is sampled on the rising edge of TCLK.
The Transmit Start of Transfer (TSX) signal is an active high
signal that marks the first cycle of a data-block transfer on the
TDAT[15:0] bus. When the TSX signal is active, the coinciding data
on the TDAT[15:0] bus represents the in-band PHY address.
The TSX output is sampled on the rising edge of TCLK.
The Transmit Cell Data (TDAT[15:0]) signals carry the ATM cell
octets that are transferred to the internal cell buffer. When this
interface is operating in 8-bit mode, only TDAT[7:0] is used.
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
Input
H21
H20
F19
G22
G21
F22
G20
F21
E22
C20
E21
C22
E20
D21
C21
B22
The TDAT[15:0] input bus is sampled on the rising edge of TCLK.
The Transmit Parity (TPRTY) signal provides the parity
TPRTY
Input
D20
(programmable for odd or even parity) of the TDAT[15:0] bus. The
TPRTY signal is considered valid only when valid data and inband
address are transferring as indicated by the TENB signal asserted
low or the TSX signal asserted high. When this interface is operating
in 8-bit mode, this signal provides the parity of TDAT[7:0].
A parity error is indicated by a status bit and a maskable interrupt.
The TPRTY input signal is sampled on the rising edge of TCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
33
PMC [ PMC-SIERRA, INC ]
