S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Pin Name Type
Pin No.
Y7
Function
The System Clock (SYSCLK) signal is the master clock for
the S/UNI-IMA-4 device. The core S/UNI-IMA-4 logic
(including the SDRAM interface) is timed to this signal.
SYSCLK
Input
External SDRAM devices share this clock and must have
clocks aligned within 0.2ns skew of the clock seen by the
S/UNI-IMA-4 device.
This clock must be stable prior to deasserting RSTB 0->1.
The Reference Clock (REFCLK) signal is an externally
REFCLK
Input
N2
generated clock with a nominal 50% duty cycle.
In CLK/Data mode, REFCLK is required and may be operated
at frequencies up to 52 MHz. In general, for T1 and E1 links,
33 MHz is sufficient. See ”Rules for Choosing Clock
frequencies” in section 13.3.1 for details on selecting the
proper frequency.
No Connect. This signal ball is not connected to the die.
NC
M2
N1
N3
P4
P1
L4
B2
A1
Reserved
C2 B1
D2 E3
C1 D1
E2 F3
L3 L2
M1 M3
N4 W2
Y2 AA1
W3 AB1
Y4 AB2
AA4 AB3
AB4 AA5
Y6 Y3
AB5 AA6
W5 W19
AB20 AA19
AA20 Y19
AA21 A20
A19 B8
C8 B7
A6 D6
C7 B6
A5 C6
B5 A4
C5 A2
A3 B3
C4 W12
AA8 H4
J3 J2 J1
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
40
PMC [ PMC-SIERRA, INC ]
