S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin
No.
Function
The Receive Serial Clock (RSCLK[3:0]) signals contain the
recovered line clock for the 4 independently timed links. The
RSDATA[3:0] signals are sampled on the rising edge of the
corresponding RSCLK[3:0] clock.
RSCLK[3]
RSCLK[2]
RSCLK[1]
RSCLK[0]
Input
R1
T4
P3
P2
For channelized T1 or E1 links, RSCLK[n] must be gapped during
the framing bit (for T1 interfaces) or during time-slot 0 (for E1
interfaces) of the RSDATA[n] stream. The S/UNI-IMA-4 uses the
gapping information to determine the time-slot alignment in the
receive stream. RSCLK[3:0] is nominally a 50% duty cycle clock of
1.544 MHz for T1 links and 2.048 MHz for E1 links.
For unchannelized links, RSCLK[n] must be externally gapped
during the bits or time-slots that are not part of the transmission
format payload (i.e., not part of the ATM cell).
The RSCLK[3:0] input signal is nominally a 50% duty cycle clock of
1.544 MHz for T1 links and 2.048 MHz for E1 links.
The RSCLK[3:0] may operate at higher rates in the unchannelized
mode. At higher rates, the amount of lines available is limited See
section 13.3.1 for more details.
The Receive Serial Data (RSDATA[3:0]) signals contain the
RSDATA[3]
RSDATA[2]
RSDATA[1]
RSDATA[0]
Input
U1
T1
R3
R2
recovered line data for the 4 independently timed links.
For channelized links, RSDATA[n] contains the 24 (T1) or 31 (E1)
time-slots that comprise the channelized link. RSCLK[n] must be
gapped during the T1 framing bit position or the E1 frame alignment
signal (time-slot 0). The S/UNI-IMA-4 uses the location of the gap to
determine the channel alignment on RSDATA[n].
For unchannelized links, RSDATA[n] contains the ATM cell data.
For certain transmission formats, RSDATA[n] may contain place-
holder bits or time-slots. RSCLK[n] must be externally gapped
during the place-holder positions in the RSDATA[n] stream.
The RSDATA[3:0] input signals are sampled on the rising edge of
the corresponding RSCLK[3:0] clock.
The Common Transmit Serial Clock (CTSCLK) signal is a
common transmit line clock that can optionally be used by all 4
serial links instead of each link’s transmit serial line clock
(TSCLK[n]). Ground if not used.
CTSCLK
Input
H2
The CTSCLK input signal is nominally a 50% duty cycle clock of
1.544 MHz for T1 links and 2.048 MHz for E1 links.
9.8 General (5 signals)
Pin Name Type
Pin No.
Function
The Reset Bar (RSTB) is an active low signal that provides an
asynchronous S/UNI-IMA-4 reset. RSTB is a Schmitt-triggered
input with an internal pull-up resistor.
RSTB
Input
AA18
The Output Enable (OE) is an active high signal that allows
all of the outputs of the device to operate in their functional
state. When this signal is low, all outputs of the S/UNI-IMA-4
go to the high impedance state, with the exception of TDO.
OE
Input
AB19
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
39
PMC [ PMC-SIERRA, INC ]
