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PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
Pin Name Type  
TPRTY Input  
Pin  
No.  
D20  
Function  
The Transmit Parity (TPRTY) signal provides the parity  
(programmable for odd or even parity) of the TDAT[15:0] bus. The  
TPRTY signal is considered valid only when valid data is  
transferring as indicated by the TENB signal asserted low. When  
this interface is operating in 8-bit mode, this signal provides the  
parity of TDAT[7:0].  
A parity error is indicated by a status bit and a maskable interrupt.  
The TPRTY input signal is sampled on the rising edge of TCLK.  
9.5 Microprocessor Interface (31 Signals)  
Pin Name Type  
Pin  
Function  
No.  
The Micro Data (D[15:0]) signals provide a data bus to allow the  
S/UNI-IMA-4 device to interface to an external microprocessor. Both  
read and write transactions are supported. The microprocessor  
interface is used to configure and monitor the S/UNI-IMA-4 device.  
D[15]  
D[14]  
D[13]  
D[12]  
D[11]  
D[10]  
D[9]  
I/O  
B18  
B17  
D18  
C16  
A17  
B16  
C15  
D17  
A16  
B15  
A15  
B14  
A14  
D14  
C13  
B13  
D[8]  
D[7]  
D[6]  
D[5]  
D[4]  
D[3]  
D[2]  
D[1]  
D[0]  
The Micro Address (A[10:1]) signals provide an address bus to  
allow the S/UNI-IMA-4 device to interface to an external  
microprocessor.  
A[10]  
A[9]  
A[8]  
A[7]  
A[6]  
A[5]  
A[4]  
A[3]  
A[2]  
A[1]  
Input  
A13  
D13  
C12  
B12  
D12  
A11  
B11  
D10  
A10  
B10  
The A[10:1] indicate a word address. The S/UNI-IMA-4  
microprocessor interface is not byte addressable.  
The A[10:1] input signals are sampled while the ALE is asserted  
high.  
The Address Latch Enable (ALE) is an active high signal that  
latches the A[10:1] signals during the address phase of a bus  
transaction. When ALE is set high, the address latches are  
transparent. When ALE is set low, the address latches hold the  
address provided on A[10:1].  
ALE  
Input  
Input  
C10  
The ALE input has an internal pull-up resistor.  
The Write Strobe Bar (WRB) is an active low signal that qualifies  
write accesses to the S/UNI-IMA-4 device. When the CSB is set low,  
the D[15:0] bus contents are clocked into the addressed register on  
the rising edge of WRB.  
WRB  
D9  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
35  
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