欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7348的Datasheet PDF文件第28页浏览型号PM7348的Datasheet PDF文件第29页浏览型号PM7348的Datasheet PDF文件第30页浏览型号PM7348的Datasheet PDF文件第31页浏览型号PM7348的Datasheet PDF文件第33页浏览型号PM7348的Datasheet PDF文件第34页浏览型号PM7348的Datasheet PDF文件第35页浏览型号PM7348的Datasheet PDF文件第36页  
S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
Pin Name Type  
Pin  
No.  
Function  
The Receive Start of Cell (RSOC) is an active high signal that  
RSOC  
Tristate  
Output  
V19  
marks the first word of the cell on the RDAT[15:0] bus.  
The RSOC output is updated on the rising edge of RCLK.  
The Receive Cell Data (RDAT[15:0]) signals carry the ATM cell  
words that have been read from the S/UNI-IMA-4 internal cell  
buffers. When this interface is operating in 8-bit mode, the data is  
carried on RDAT[7:0].  
RDAT[15]  
RDAT[14]  
RDAT[13]  
RDAT[12]  
RDAT[11]  
RDAT[10]  
RDAT[9]  
RDAT[8]  
RDAT[7]  
RDAT[6]  
RDAT[5]  
RDAT[4]  
RDAT[3]  
RDAT[2]  
RDAT[1]  
RDAT[0]  
Tristate  
Output  
U22  
T22  
U19  
R20  
R22  
T19  
R19  
P20  
P21  
P22  
P19  
N20  
N21  
N22  
N19  
M20  
The RDAT[15:0] output bus is updated on the rising edge of RCLK.  
The Receive Parity (RPRTY) signal provides the parity  
(programmable for odd or even parity) of the RDAT[15:0] bus. When  
the interface is operating in 8-bit mode, the parity is calculated over  
RDAT[7:0]  
RPRTY  
Tristate  
Output  
M22  
The RPRTY output is updated on the rising edge of RCLK.  
9.3 Transmit Slave Interface (ANY-PHY mode) (30 Signals)  
Pin Name Type  
Pin  
Function  
No.  
The Transmit Clock (TCLK) signal is used to transfer cells across  
TCLK  
Input  
E19  
the ANY-PHY interface to the internal downstream cell buffers.  
The TPA output is updated on the rising edge of TCLK.  
The TENB. TSX, TSOP, TDAT[15:0], TPRTY, TADR[6:0], and  
TCSB inputs are sampled on the rising edge of TCLK.  
The TCLK input must cycle at a 52 MHz or lower instantaneous rate.  
The Transmit Packet Available (TPA) is an active high signal that  
indicates the availability of space in the selected logical channel  
FIFO when polled using the TADR[6:0] signals.  
TPA  
Tristate  
Output  
L22  
The S/UNI-IMA-4 device drives TPA with the cell availability status  
of the polled port two TCLK cycles after TADR[6:0] matches the  
S/UNI IMA’s device address. The TPA output is high-impedance at  
all other times.  
The TPA output is updated on the rising edge of TCLK.  
The Transmit enable bar (TENB) is an active low signal that is  
TENB  
Input  
L20  
used to indicate cell transfers to the internal cell buffers.  
The TENB input is sampled on the rising edge of TCLK.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
32  
 复制成功!