S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
9
Pin Description
9.1 Receive Slave ATM Interface (Any-PHY mode) (28 Signals)
Pin Name Type
Pin
Function
No.
The Receive Clock (RCLK) signal is used to transfer data blocks
RCLK
Input
T21
from the S/UNI-IMA-4 across the receive Any-PHY interface.
The RPA, RSOP, RSX, RDAT[15:0], and RPRTY outputs are
updated on the rising edge of RCLK. The RENB, RADR[4:0], and
RCSB inputs are sampled on the rising edge of RCLK.
The RCLK input must cycle at a 52 MHz or lower instantaneous
rate.
The Receive Packet Available (RPA) is an active high signal that
RPA
Tristate
Output
AB22
W20
indicates whether at least one cell is queued for transfer.
The S/UNI-IMA-4 device drives the RPA with the cell availability
status two RCLK cycles after RADR[4:0] matches the S/UNI IMA’s
device address. The RPA output is high-impedance at all other
times.
The RPA output is updated on the rising edge of RCLK.
The Receive Enable Bar (RENB) is an active low signal used to
initiate the transfer of cells from the S/UNI-IMA-4 to an ATM layer
component, such as a traffic management device.
RENB
Input
Input
The RENB input is sampled on the rising edge of RCLK.
The Receive Address (RADR[4:0]) signals are used to address the
S/UNI-IMA-4 device for the purposes of polling and selection for cell
transfer. The RADR[4:0] signals are valid only when the RCSB
signal is sampled active in the following RCLK cycle.
RADR[4]
RADR[3]
RADR[2]
RADR[1]
RADR[0]
AA22
Y21
V20
Y22
W22
The RADR[4:0] input bus is sampled on the rising edge of RCLK.
The Receive Chip Select (RCSB) is an active low signal that is
used to select the S/UNI-IMA-4 receive interface. When the RCSB is
sampled low, it indicates that the RADR[4:0] sampled at the
previous clock is a valid address. If the RCSB is sampled high, the
device is not selected and the RADR[4:0] sampled on the previous
cycle is not a valid address and is ignored. When sufficient address
space is provided by RADR[4:0] for all devices on the bus, this
signal may be tied low.
RCSB
Input
U21
The RCSB input is sampled on the rising edge of RCLK.
The Receive Start of Packet (RSOP) is an active high signal that
marks the start of the cell on the RDAT[15:0] bus. When RSOP is
active, the first word of the cell is present on the RDAT[15:0] bus.
RSOP
RSX
Tristate
Output
V19
T20
The RSOP output is updated on the rising edge of RCLK.
The Receive Start of Transfer (RSX) signal is an active high signal
that marks the first cycle of a data block transfer on the RDAT[15:0]
bus. When the RSX signal is active, the coinciding data on the
RDAT[15:0] bus represents the in-band PHY address.
Tristate
Output
The RSX output is updated on the rising edge of RCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
30
PMC [ PMC-SIERRA, INC ]
