Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Symbol
Parameter
CLK enable hold time
Signals
Min
Max
Unit
Tckh
DRAM_CKE
DRAM_CKE
*
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tcksu
Trassu
Trash
Tcassu
Tcash
Tcssu
Tcsh
CLK enable setup time
RAS setup time
*
/TX_DRAM_RAS
3.3
1.5
3.3
1.5
2.7
1.5
2.9
1.5
2.2
1.5
RAS hold time
/TX_DRAM_RAS
/TX_DRAM_CAS
CAS setup time
CAS hold time
/TX_DRAM_CAS
/TX_DRAM_CS(1:0)
/TX_DRAM_CS(1:0)
/TX_DRAM_WE
Chip select setup time
Chip select hold time
Write enable setup time
Write enable hold time
Twesu
Tweh
Tdsu
/TX_DRAM_WE
(Write) Data valid before clock
(Write) Data Valid after clock
TX_DRAM_DATA(31:0)
TX_DRAM_DATA(31:0)
Tdh
* The DRAM_CKE is a functionally static signal. Software should ensure that the DRAM_CKE
is set at least 1 microsecond before desserting the SW_RESET bit.
6.3 SRAM Timings
All inputs and outputs are assume to have a 30 pf capacitive loading. The ALRAM_CLK,
ABRAM_CLK and CHRAM_CLK are assume to have a 22 ohm series terminated resister
connected to a combined capacitive load of 36 pf.
Figure 56 shows the AL RAM read timing.
ALRAM READ CYCLE
1
2
3
4
5
Tcyc
Tch
Tcl
ALRAM_CLK
Tadh
Tadss
/ALRAM_ADSC
/ALRAM_OE
Toesu
Toeh
Tadrh
Tadh
Tadrh
Tweh
Tadrsu
Tadrsu
Tadrsu
Twesu
ALRAM_ADD(18:0)
ALRAMADD17N
ALRAMADD18N
/ALRAM_WE
Trdh
Trds
VALID DATA
ALRAM_DATA(16:0)
Figure 56. Address Lookup RAM Read Timing
83
PMC [ PMC-SIERRA, INC ]
