Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Symbol
Parameter
Signals
CH_RAM_CLK
Min
Max
Units
Tcyc
Tch
Tcl
Clock period
10
3
ns
ns
ns
ns
Clock high period
Clock low period
Address setup time
CH_RAM_CLK
CH_RAM_CLK
3
Tas
CH_RAM_ADD(17:0),
CH_RAM_ADD17N
3.1
Tah
Address hold time
CH_RAM_ADD(17:0),
CH_RAM_ADD17N
1
ns
Toesu
Toeh
Tadss
Tadh
Trds
Output enable setup time
Output enable hold time
Address strobe setup time
Address strobe hold time
/CH_RAM_OE
3.5
-1
ns
ns
ns
ns
ns
ns
ns
ns
/CH_RAM_OE
/CH_RAM_ADSC
/CH_RAM_ADSC
CH_RAM_DATA(31:0)
CH_RAM_DATA(31:0)
/CH_RAM_WE
3.2
1
(Read) Data valid required before clock
(Read) Data valid required after clock
Write enable setup time
4.7
1
Trdh
Twesu
Tweh
3.3
1
Write enable hold time
/CH_RAM_WE
Figure 59 shows the channel RAM write timing.
CHRAM WRITE CYCLE
1
2
3
4
5
Tcyc
Tch
Tcl
CH_RAM_CLK
Tadh
Toeh
Tadss
Toesu
/CH_RAM_ADSC
/CH_RAM_OE
CH_RAM_ADD(17:0)
CH_RAM_ADD17N
Tas
Tah
Tah
Tas
Tweh
Twesu
Tds
/CH_RAM_WE
CH_RAM_DATA(31:0)
CH_RAM_PARITY0
CH_RAM_PARITY1
Tdh
Tdh
Tdh
VALID DATA
Tds
Tds
Figure 59. Channel RAM Write Timing
86
PMC [ PMC-SIERRA, INC ]
