Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
6.2 DRAM External Memory Timing
NOTE: All inputs are the minimum required. All outputs are the minimum expected. All inputs and outputs
are assume to have a 30 pf capacitive loading. The RX_DRAM_CLK and TX_DRAM_CLK are
assume to have a 22 ohm series terminated resister connected to a combined capacitive load of 36
pf.
Figure 52 shows the receive DRAM external memory 100 MHz read timing.
Tch
Tcyc
Tcl
RX_DRAM_CLK
DRAM_CKE
Tckh
Tcksu
Tcsh
Tcssu
/RX_DRAM_CS(1:0)
/RX_DRAM_RAS
/RX_DRAM_CAS
RX_DRAM_ADD(8:0)
/RX_DRAM_WE
Trash
Trassu
Tcash
Tcassu
Taddrh
Taddrsu
ROW
COLUMN
Tweh
Twesu
Trdh
Trds
RX_DRAM_DATA(31:0)
RX_DRAM_BA
VALID DATA
Tbah
Tbasu
Figure 52. Receive DRAM External Memory 100 MHz Read Timing
Symbol
Parameter
Signals
RX_DRAM_CLK
Min
Max
Unit
Tcyc
Clock period
Clock high period
10
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tch
RX_DRAM_CLK
RX_DRAM_CLK
RX_DRAM_ADD(8:0)
RX_DRAM_BA
Tcl
Clock low period
Address setup time
Bank address setup time
Address hold time
Bank address hold time
Enable hold time *
Enable setup time *
RAS setup time
3
Taddrsu
Tbasu
Taddrh
Tbah
2.7
2.9
1.3
1.5
RX_DRAM_ADD(8:0)
RX_DRAM_BA
Tckh
DRAM_CKE
Tcksu
Trassu
Trash
Tcassu
Tcash
Tcssu
Tcsh
DRAM_CKE
/RX_DRAM_RAS
/RX_DRAM_RAS
/RX_DRAM_CAS
/RX_DRAM_CAS
/RX_DRAM_CS(1:0)
/RX_DRAM_CS(1:0)
3.1
1.5
3.2
1.5
2.4
2.2
2.7
RAS hold time
CAS setup time
CAS hold time
Chip select setup time
Chip select hold time
Trdh
Required hold time required (read data) RX_DRAM_DATA(31:0)
79
PMC [ PMC-SIERRA, INC ]
