Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Symbol
Parameter
Signals
/RX_DRAM_WE
Min
Max
Unit
Twesu
Tweh
Tdsu
Tdh
Write enable setup time
Write enable setup time
2.8
1.5
2.4
1
ns
ns
ns
ns
/RX_DRAM_WE
(Write) Data valid before clock
(Write) Data valid after clock
RX_DRAM_DATA(31:0)
RX_DRAM_DATA(31:0)
* The DRAM_CKE is a functionally static signal. Software should ensure that the DRAM_CKE
is set at least 1 microsecond before desserting the SW_RESET bit.
Figure 54 shows the transmit DRAM external memory 100 MHz read timing.
TX DRAM READ CYCLE
1
2
3
4
5
6
7
8
Tch
Tcyc
Tcl
TX_DRAM_CLK
DRAM_CKE
Tckh
Tcksu
Tcsh
Tcssu
/TX_DRAM_CS(1:0)
/TX_DRAM_RAS
/TX_DRAM_CAS
TX_DRAM_ADD(8:0)
/TX_DRAM_WE
Trash
Trassu
Tcash
Tcassu
Taddrh
Taddrsu
ROW
COLUMN
Tweh
Twesu
Trdh
Trds
VALID DATA
TX_DRAM_DATA(31:0)
TX_DRAM_BA
Tbah
Tbasu
Figure 54. Transmit DRAM External Memory 100 MHz Read Timing
Symbol
Parameter
Signals
TX_DRAM_CLK
Min
Max
Unit
Tcyc
Clock period
10
3
ns
ns
ns
ns
ns
ns
ns
ns
Tch
Clock high period
TX_DRAM_CLK
TX_DRAM_CLK
TX_DRAM_ADD(8:0)
TX_DRAM_ADD(8:0)
TX_DRAM_BA
Tcl
Clock low period
3
Taddrsu
Taddrh
Tbasu
Tbah
Tckh
Address setup time
Address hold time
3.1
1.3
2.8
1.5
*
Bank address setup time
Bank address hold time
Clock enable hold time
TX_DRAM_BA
DRAM_CKE
81
PMC [ PMC-SIERRA, INC ]
