Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Symbol
Parameter
Signals
CH_RAM_CLK
Min
Max
Units
Tcyc
Tch
Tcl
Clock period
10
3
ns
ns
ns
ns
Clock high period
Clock low period
Address setup time
CH_RAM_CLK
CH_RAM_CLK
3
Tas
CH_RAM_ADD(17:0),
CH_RAM_ADD17N
3.1
Tah
Address hold time
CH_RAM_ADD(17:0),
CH_RAM_ADD17N
0.8
ns
Toesu
Toeh
Tadss
Tadh
Tds
Output enable setup time
Output enable hold time
Address strobe setup time
Address strobe hold time
/CH_RAM_OE
3.5
-1
ns
ns
ns
ns
ns
ns
ns
ns
/CH_RAM_OE
/CH_RAM_ADSC
/CH_RAM_ADSC
CH_RAM_DATA
CH_RAM_DATA
/CH_RAM_WE
/CH_RAM_WE
3.2
1
(Write) Data valid before clock
(Write) Data valid after clock
Write enable setup time
2.5
1
Tdh
Twesu
Tweh
3.3
1
Write enable hold time
Figure 60 shows the AB RAM read timing.
ABRAM READ CYCLE
1
2
3
4
5
Tcyc
Tch
Tcl
ABR_RAM_CLK
Tadsph
Tadspsu
/ABR_RAM_ADSP
/ABR_RAM_OE
Toesu
Toeh
Tadrh
Tadrsu
Twesu
Trds
Data 1
Trdh
ABR_RAM_AD(16:0)
/ABR_RAM_WE
Address
Data 2
Tweh
Tadvnh
Tadvnsu
/ABR_RAM_ADV
Figure 60. AB RAM Read Timing
87
PMC [ PMC-SIERRA, INC ]
