Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Symbol
Parameter
Signals
Min
Max
Unit
Tcksu
Trassu
Trash
Tcassu
Tcash
Tcssu
Tcsh
Clock enable setup time
RAS setup time
DRAM_CKE
*
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/TX_DRAM_RAS
/TX_DRAM_RAS
/TX_DRAM_CAS
/TX_DRAM_CAS
/TX_DRAM_CS(1:0)
/TX_DRAM_CS(1:0)
TX_DRAM_DATA(31:0)
/TX_DRAM_WE
3.3
1.5
3.3
1.5
2.7
1.5
2
RAS hold time
CAS setup time
CAS hold time
Chip select setup time
Chips select hold time
Trdh
(Read) Data Valid required after clock
Write enable setup time
Twesu
Tweh
Trds
2.9
1.5
0
Write enable hold time
/TX_DRAM_WE
(Read) Data valid required before clock TX_DRAM_DATA(31:0)
Figure 55 shows the transmit DRAM external memory 100 MHz write timing.
Tch
Tcyc
Tcl
TX_DRAM_CLK
DRAM_CKE
Tckh
Tcksu
Tcsh
Tcssu
/TX_DRAM_CS(1:0)
/TX_DRAM_RAS
/TX_DRAM_CAS
TX_DRAM_ADD(8:0)
/TX_DRAM_WE
Trash
Trassu
Tcash
Tcassu
Taddrh
Taddrsu
ROW
COLUMN
Tweh
Twesu
Tdh
Tdsu
TX_DRAM_DATA(31:0)
TX_DRAM_BA
VALID DATA
VALID DATA
VALID DATA
VALID DATA
Tbah
Tbasu
Figure 55. Transmit DRAM External Memory 100 MHz Write Timing
Symbol
Parameter
Signals
TX_DRAM_CLK
Min
Max
Unit
Tcyc
TX_DRAM_CLK period
TX_DRAM_CLK high period
TX_DRAM_CLK low period
Address setup time
10
3
ns
ns
ns
ns
ns
ns
ns
Tch
TX_DRAM_CLK
TX_DRAM_CLK
TX_DRAM_ADD(8:0)
TX_DRAM_ADD(8:0)
TX_DRAM_BA
Tcl
3
Taddrsu
Taddrh
Tbasu
Tbah
3.1
1.3
2.8
1.5
Address hold time
Bank address setup time
Bank address hold time
TX_DRAM_BA
82
PMC [ PMC-SIERRA, INC ]
