Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Symbol
Parameter
Signals
/RX_DRAM_WE
Min
Max
Unit
Twesu
Tweh
Trds
Write enable setup time
Write enable hold time
2.8
1.5
0
ns
ns
ns
/RX_DRAM_WE
Required setup time (read data)
RX_DRAM_DATA(31:0)
Figure 53 shows the receive DRAM external memory 100 MHz write timing.
Tch
Tcyc
Tcl
RX_DRAM_CLK
DRAM_CKE
Tckh
Tcksu
Tcsh
Tcssu
/RX_DRAM_CS(1:0)
/RX_DRAM_RAS
/RX_DRAM_CAS
RX_DRAM_ADD(8:0)
/RX_DRAM_WE
Trash
Trassu
Tcash
Tcassu
Taddrh
Taddrsu
ROW
COLUMN
Tweh
Twesu
Tdsu
Tdh
RX_DRAM_DATA(31:0)
RX_DRAM_BA
VALID DATA
VALID DATA
VALID DATA
Tbah
Tbasu
Figure 53. Receive DRAM External Memory 100 MHz Write Timing
Symbol
Parameter
Signals
RX_DRAM_CLK
Min
Max
Unit
Tcyc
Clock period
Clock high period
10
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tch
RX_DRAM_CLK
RX_DRAM_CLK
RX_DRAM_ADD(8:0)
RX_DRAM_ADD(8:0)
RX_DRAM_BA
Tcl
Clock low period
3
Taddrsu
Taddrh
Tbasu
Tbah
Address setup time
Address hold time
Bank address setup time
Bank address hold time
Clock enable hold time *
Clock enable setup time *
RAS setup time
2.7
1.3
2.9
1.5
*
RX_DRAM_BA
Tckh
DRAM_CKE
Tcksu
Trassu
Trash
Tcassu
Tcash
Tcssu
Tcsh
DRAM_CKE
*
/RX_DRAM_RAS
/RX_DRAM_RAS
/RX_DRAM_CAS
/RX_DRAM_CAS
/RX_DRAM_CS(1:0)
/RX_DRAM_CS(1:0)
3.1
1.5
3.2
1.5
2.4
2.2
RAS hold time
CAS setup time
CAS hold time
Chip select setup time
Chip select hold time
80
PMC [ PMC-SIERRA, INC ]
