Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
(Continued)
Field (Bits)
Description
RX_DRAM_ADDRESS
(24:16)
Corresponds to the row address during active cycles and column address during READ
or WRITE cycles. The MSB is autoprecharge during Channel Associated Signaling
(CAS) cycles (READ or WRITE).
RX_DRAM_UPPER_ADDR
(15:14)
For SGRAM:
Buffer RAM is organized as 2 chips with 512 rows each
00b Select SGRAM chip 0.
01b Select SGRAM chip 1.
10b Invalid.
11b Invalid.
For SDRAM:
Buffer RAM is organized as 2048 rows
00b Select Rows 0 to 511
01b Select Rows 512 to 1023.
10b Select Rows 1024 to 1535
11b Select Rows 1536 to 2047
Reserved
(13:0)
Initialize to 0 at initial setup. Software modifications to this location after setup may
cause incorrect operation.
200
PMC [ PMC-SIERRA, INC ]
