Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
9.5.2 TX_DRAM_REGISTER
Address: 3000000h (C000000h byte)
Type: Read/Write
Field (Bits)
Description
TX_DRAM_ACCESS_CODE
The access code to control the type of SDRAM/SGRAM cycle.
(31:28)
TX_DRAM_DATA
(27:26)
The data to be written to the SDRAM/SGRAM. This 2-bit field is replicated 16 times
and written to the 32-bit wide SDRAM/SGRAM. Data of 00, 01, 10, and 11 correspond
to DRAM data 00000000h, 55555555h, AAAAAAAAh, and FFFFFFFFh. No other val-
ues of data can be written to the SDRAM/SGRAM.
TX_DRAM_MI_SELECT
(25)
Select for microprocessor access to the SDRAM/SGRAM. Write with a 0 for normal
operation.
TX_DRAM_ADDRESS
(24:16)
Corresponds to the row address during ACTIVE cycles and column address during
READ or WRITE cycles. The MSB is autoprecharge during CAS cycles (READ or
WRITE).
TX_DRAM_UPPER_ADDR
(15:14)
For SGRAM:
Buffer RAM is organized as 2 chips with 512 rows each
00b Select SGRAM chip 0.
01b Select SGRAM chip 1.
10b Invalid.
11b Invalid.
For SDRAM:
Buffer RAM is organized as 2048 rows
00b Select Rows 0 to 511
01b Select Rows 512 to 1023.
10b Select Rows 1024 to 1535
11b Select Rows 1536 to 2047
Reserved
(13:0)
Initialize to 0 at initial setup. Software modifications to this location after setup may
cause incorrect operation.
201
PMC [ PMC-SIERRA, INC ]
