Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
After powerup or after a sustained software reset, the transmit and receive SDRAMs/SGRAMs
need to be initialized. The RX_DRAM_REGISTER runs in a burst-of-four mode, whereas the
TX_DRAM_REGISTER runs in a burst-of-eight mode, so the MODE register needs to be initial-
ized differently.
To initialize the SDRAM/SGRAM:
W-No op
Chip 0
Chip 1(SGRAM only)
00004000h
93004000h
A2004000h
A2004000h
00000000h
93000000h
A2000000h
A2000000h
W-Precharge both banks
W-Autorefresh
W-Autorefresh
W-Load
register
C2YY
(YY = 32
for
RX_DRAM_REGISTER,
33
for
TX_DRAM_REGISTER)
C2320000h
00000000h
C2324000h
00004000h
W-No op
To write a location to the SDRAM/SGRAM (for example, location 0h in bank 0 with 55555555h):
W-Active bank 0
W-Write bank 0
32000000h
26000000h
32004000h
26004000h
To read the location of the SDRAM/SGRAM (for example, location 0h in bank 0):
W-Active bank 0
W-Read bank 0
R-
32000000h
12000000h
value of the DRAM location
32004000h
12004000h
To write a location to the SDRAM/SGRAM (for example, location 1234h in bank 1with
AAAAAAAAh):
W-Active bank 1
W-Write bank 1
72120000h
6A340000h
72124000h
6A344000h
9.5.1 RX_DRAM_REGISTER
Address: 2000000h (8000000h byte)
Type: Read/Write
Field (Bits)
Description
RX_DRAM_ACCESS_CODE
(31:28)
The access code to control the type of SDRAM/SGRAM cycle.
RX_DRAM_DATA
(27:26)
The data to be written to the DRAM. This 2-bit field is replicated 16 times and written
to the 32-bit wide SDRAM/SGRAM. Data of 00, 01, 10, and 11 correspond to DRAM
data 00000000h, 55555555h, AAAAAAAAh, and FFFFFFFFh. No other values of data
can be written to the SDRAM/SGRAM.
RX_DRAM_MI_SELECT
(25)
0
1
Normal operation.
Enables microprocessor access to the SDRAM/SGRAM.
199
PMC [ PMC-SIERRA, INC ]
