Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
9.4 ABR_RAM
Table 42 summarizes the contents of the AB_RAM.
Table 42. AB_RAM Summary
Byte
Offset
Long
Offset
Read or
Write
Name
Description
0180000h 600000h Receive Channel Queue Block
R/W
R/W
Receive channel head and tail pointers.
Receive channel sent/drop cell counters
0184000h 610000h Receive Channel Sent/Drop
counters
9.4.1 Receive Channel Queue Block
Base address: 600000h (0180000h byte)
Index: 2h
The long address = 600000h + RX_CHAN_NUM × 2h+ long_offset
Table 43. Receive Channel Queue Block Summary
Address
Name
RX_CH_HEAD
Read or Write
Description
0h
R/W
Head pointer of the receive
channel queue.
1h
RX_CH_TAIL
R/W
Tail pointer of the receive
channel queue.
9.4.1.1 RX_CH_HEAD (Internal Structure)
Offset: 0h (0h byte)
Type: Read/Write
Format: Refer to the following table.
Field (Bits)
Description
No RAM is present in these bit positions.
Not present
(31:16)
RX_QUEUE_HEAD
(15:0)
The head of the channel queue.
9.4.1.2 RX_CH_TAIL (Internal Structure)
Offset: 1h (4h byte)
Type: Read/Write
Format: Refer to the following table.
Field (Bits)
Description
No RAM is present in these bit positions.
Not present
(31:16)
RX_QUEUE_TAIL
(15:0)
The tail of the channel queue.
196