Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
9.4.2 Receive Channel Statistics Block
Base address: 610000h (0184000h byte)
Index: 4h
The long address = 610000h + RX_CHAN_NUM × 4h+ long_offset
The receive channel statistics counters are only valid if the RX_STATS bit in the
RX_QUEUE_ENGINE_TEST register (“RX_QUEUE_ENGINE_TEST” on
page 123) is set to 1
Table 44. Receive Channel Queue Block Summary
Address
Name
RX_CH_SENT
Read or Write
Description
0h
R/W
Cells sent from this chan-
nel.
2h
RX_CH_DROPPED
R/W
Cells dropped from this
channel.
9.4.2.1 RX_CH_SENT (Internal Structure)
Offset: 0h (0h byte)
Type: Read/Write
Format: Refer to the following table.
Field (Bits)
Description
Total cells sent from this channel. Initialize to 0
RX_CH_SENT
(31:0)
9.4.2.2 RX_CH_DROPPED (Internal Structure)
Offset: 2h (8h byte)
Type: Read/Write
Format: Refer to the following table.
Field (Bits)
Description
Total cells dropped from this channel. initialize to 0
RX_CH_DROPPED
(31:0)
9.5 SDRAM/SGRAM Interface Description
The SDRAMs/SGRAMs are used in the QRT system to store the cells in the receive and transmit
directions. Before the SDRAMs/SGRAMs can be used, they must be prepared for operation. This
section discusses setting up the SDRAM/SGRAM for normal operations, as well as test mode
access by the microprocessor to check the data integrity of the SDRAM/SGRAM.
197
PMC [ PMC-SIERRA, INC ]
