Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
10 JTAG
JTAG Support
The QRT supports the IEEE Boundary Scan Specification as described in the
IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard
pins, TRSTB, TCK, TMS, TDI and TDO, used to control the TAP controller and the
boundary scan registers. The TRSTB input is the active low reset signal used to
reset the TAP controller. TCK is the test clock used to sample data on input, TDI
and to output data on output, TDO. The TMS input is used to direct the TAP con-
troller through its states. The basic boundary scan architecture is shown below.
Figure 70. Boundary Scan Architecture
Boundary Scan
TDI
Register
Device Identification
Register
Bypass
Register
Instruction
Mux
Register
DFF
TDO
and
Decode
Control
TMS
Test
Access
Port
Select
Controller
Tri-state Enable
TRSTB
TCK
The boundary scan architecture consists of a TAP controller, an instruction regis-
ter with instruction decode, a bypass register, a device identification register and a
boundary scan register. The TAP controller interprets the TMS input and gener-
ates control signals to load the instruction and data registers. The instruction reg-
ister with instruction decode block is used to select the test to be executed and/or
the register to be accessed. The bypass register offers a single bit delay from pri-
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PMC [ PMC-SIERRA, INC ]
